AUTHORS: G. Durga, M. Meryl Rino
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ABSTRACT: The presence of radiation in space environment causes effects in modern electronic devices. This effects range from degradation of performance to functional failures. One of the radiation effects is SEE (Single-event effects). This work presents a design of D and S-R flip flop as variant of the Dual Interlocked storage Cell (DICE) which is tolerant to a single event double upset (SEDU). The design is referred to as modified transistor DICE (TDICE) which uses PMOS and NMOS transistors as a feedback transistors to block the paths that connect a node to the next node. The use of these transistors hardens the cell to tolerate a single event double upset with critical charge at a large value. Extensive simulation results are provided to assess modified TDICE with respect to traditional circuit figures of merit such as number of transistors, power consumption, and delay. The simulation results show the expense of an increased area for the additional transistors, modified TDICE shows a nearly complete tolerance to a single event double upset. All the simulations are done using Tanner EDA tool with 65nm technology
KEYWORDS: D flip flop, DICE, SET, SEU, S-R flip flop, Tanner EDA tool
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